1. Field of the Invention
The present invention relates to a machine check processing system. More particularly, it relates to a system having an error correcting function, wherein error data relating to a corrected error can be saved by a service processing unit (SVP) without substantially interrupting the system processing and the SVP can inhibit machine check interruption based on an analysis of the saved error data.
2. Description of the Prior Art
A known data processing system has a main memory, a memory control unit (MCU), a central processing unit (CPU), and an SVP. When a correctable error, for example, a single bit error, occurs during data processing, the error is corrected in the MCU. Further, in the prior art, a predetermined area in the main memory receives information (error data) relating to the single bit error, for example, the place where the single bit error occurred. The error data is stored for the purpose of providing information about the site of the single bit error to prevent problems. If the single bit error is a hard error, the possibility of an uncorrectable error, i.e., a double bit error, occurring is high. Therefore, an operator, a user, or a maintenance man needs to know the place where the single bit error occurred.
There are, however, various problems in storing error data in a predetermined area in the main memory. First, since the predetermined area in the main memory is not a large area, it cannot store a large number amount of error data. Therefore, the error data must be saved in another place or must be output to an outer device everytime the predetermined area is full of error data. This saving or outputting process is very troublesome for the user.
Second, a machine check interruption occurs during every period in which error data is stored in the predetermined area in the main memory so that data processing is interrupted during that period. In a conventional machine, to avoid machine check interruption everytime a single bit error is detected, once single bit errors have been detected several times, for example, four times, the predetermined area in the main memory is not informed of any subsequent error data so that a machine check interruption due to a single bit error does not occur after several single bit errors occur. By this method, however, the maintenance man, etc. cannot discover the site of subsequent single bit errors after several single bit errors occur.